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80a, 40v the irsm005800mh is a general purpose halfbridge with integrated gate driver in an attractive 7x8mm pqfn package. it is a general purpose building bloc k suitable for a variety of low voltage application s where power density is of critical importance. typical ex amples would be advanced motor drives, dctoac and dc todc converters. ? package with low thermal resistance and minimal pa rasitics ? low onresistance hexfets: 2.7 m typ. ? undervoltage lockout on logic supply ? independent gate drive in phase with logic input ? gate drive supply range from 10v to 20v ? propagation delay matched to defined spec ? 3.3v, 5v and 15v logic input compatible ? rohs compliant !" !#$% &% irsm005800mh pqfn 7x8mm tray 1300 irsm005800mhtr pqfn 7x8mm tape and reel 2000
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+ , absolute maximum ratings indicate sustained limits beyond which damage to the module may occur. these are not tested at manufacturing. all voltage parameter s are absolute voltages referenced to v ss unless otherwise stated in the table. the thermal resistance rating is measured under board mounted and still air cond itions. % , - ! ! " # !!! $
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&"# ! ) *% 6 6 "7 # 89! : ;#21 #<2 "2"&&=7 # ! 3 ) ;#21 #2"&&= 27 # : ! : 8 3 %% > 1$12"&&=7 # ! 3 ) > > 21 "&"7 # ! 3 %% 8 3 ; ;#21 "&"7 # ! 3 %% 8 3 , > #&"7 #>,;, ! 3 %% 8 3 note1: calculated based on maximum junction tempera ture. bond wires current limit is 49a ./ v bias (v cc , v bs )=15v, tj=25oc, unless otherwise specified. % $% , - / v (br)dss draintosource breakdown voltage 40 v h in =l in =0v, i d =250a v gs(th) gate threshold voltage 2 4 v i d =100a 2.7 5.0 i d =10a, t j =25c r ds(on) draintosource voltage 4.2 m i d =10a, t j =150c 20 h in =l in =0v, v + =40v i dss zero gate voltage drain current 150 a h in =l in =0v, v + =40v, t j =125c gate to source forward leakage 100 v gs =20v i gss gate to source reverse leakage 100 na v gs =20v r g internal gate resistance 1.5 0.8 0.9 i f =10a v sd mosfet diode forward voltage drop 0.55 v i f =10a, t j =150c rbsoa reverse bias safe operating area full square, limited by t jmax v + = 40v, v cc =+15v to 0v i o @ t a =60c rms phase current, sinusoidal modulation, 5khz 13.5 a rms i o @ t a =60c rms phase current, sinusoidal modulation, 20khz 6 a rms v+=32v, tj=125c, mi=1, pf=0.8, typical board mount. see figure 2. eas single pulse avalanche energy 9.2 mj downloaded from: http:///

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.%/ v bias (v cc , v bs )=15v, tj=25oc, unless otherwise specified. gfs forward transconductance 159 s i d =50a v ds = 10v q g total gate charge 65 98 q gs gate to source charge 16 q gd gate to drain charge 23 i d =50a v ds = 20v v gs =10v q sync total gate charge sync. (q g q gd ) 42 nc i d =50a,v ds = 0v,v gs = 10v t don mosfet turn on delay time 11 t r mosfet rise time 37 t doff mosfet turn off delay time 33 t f mosfet fall time 26 ns i d =30a v dd = 20v v gs =10v r g =2.7 c iss input capacitance 3174 c oss output capacitance 479 c rss reverse transfer capacitance 332 pf f= 1.0mhz v ds = 25v v gs =0v t rr reverse recovery time 16 ns q rr reverse recovery charge 5 nc i rrm reverse recovery current 0.5 a i f =50a v r =34v di/dt= 100a/us / . for proper operation the device should be used with in the recommended conditions. all voltages are abs olute referenced to com. the vs offset is tested with all supplies biased at 15v differential. % $% , - v b high side floating supply voltage v s +10 v s +15 v s +20 v v s high side floating supply offset voltage note 1 40 v v cc low side and logic fixed supply voltage 10 15 20 v v in logic input voltage lin, hin com v cc v hin high side pwm pulse width 1 s deadtime suggested dead time between hin and lin 0. 3 0.5 s downloaded from: http:///

/ . v bias (v cc , v bs )=15v, t j =25oc, unless otherwise specified. the v in , and i in parameters are referenced to com % $% , - $ / v ih positive going input threshold for lin, hin 2.5 v il negative going input threshold for lin, hin 0.8 v cc =10 to 20v v oh high level output voltage 0.05 0.2 i o =2ma v ol low level output voltage 0.02 0.1 v ccuv+ v bsuv+ v cc /v bs supply undervoltage, positive going threshold 8.0 8.9 9.8 v ccuv v bsuv v cc /v bs supply undervoltage, negative going threshold 7.4 8.2 9.0 v ccuvh v bsuh v cc /v bs supply undervoltage lockout hysteresis 0.8 v i lk offset supply leakage current 50 v b =v s =200v i qbs quiescent v bs supply current 45 75 i qcc quiescent v cc supply current 250 500 v in =0v or 5v i in+ input bias current v in =5v for lin, hin 4 10 v in = 5v i in input bias current v in =0v for lin, hin 0.5 1 a v in =0v i o+ ic high output short circuit current 200 290 i o ic low output short circuit current 420 600 ma v o = 0v, v in = 5v, pw <10us %/ . v bias (v cc , v bs )=15v, tj=25oc unless otherwise specified, c l = 1000 pf, driver only timing. % $% , - / t r ic turn on rise time 50 150 t f ic turn off fall time 35 90 t on ic input to output propagation turn on delay time 160 220 t off ic input to output propagation turn off delay time 150 220 mt ic delay matching, hs and ls turn on/off 50 ns downloaded from: http:///

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$/ % $% , - / r th(jb) thermal resistance, junction to mounting pad, each mosfet 3.8 c/w standard reflowsolder process r th(ja) thermal resistance, junction to ambient, each mosfet 40 c/w mounted on 50mm 2 of fourlayer fr4 with 28 vias ((.$ ;, >, ?@ ; ; ! "# > > aa ; > 8 > ; a8
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4 6 8 10 12 14 16 18 20 v gs, gate to source voltage (v) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 r d s ( o n ) , d r a i n t o s o u r c e o n r e s i s t a n c e ( m ) i d = 50a t j = 25c t j = 125c 01$% . 2* 3 4 5 6 7 8 v gs , gatetosource voltage (v) 1.0 10 100 1000 i d , d r a i n t o s o u r c e c u r r e n t ( a ) t j = 25c t j = 150c v ds = 10v 60s pulse width 03$%$ / 0.1 1 10 100 v ds , draintosource voltage (v) 1 10 100 1000 i d , d r a i n t o s o u r c e c u r r e n t ( a ) vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.5v 60s pulse widt h tj = 25c 4.5v 0$%/ 45/ 60 40 20 0 20 40 60 80 100 120 140 160 t j , junction temperature (c) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 r d s ( o n ) , d r a i n t o s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 50a v gs = 10v 05"6 . $ 0.1 1 10 100 v ds , draintosource voltage (v) 1 10 100 1000 i d , d r a i n t o s o u r c e c u r r e n t ( a ) 4.5v 60s pulse widt h tj = 150c vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.5v 07$%/ 41/ 1 10 100 v ds , draintosource voltage (v) 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 08$%/. * downloaded from: http:///

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0 10 20 30 40 50 60 70 80 90 q g , total gate charge (nc) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 v g s , g a t e t o s o u r c e v o l t a g e ( v ) v ds = 32v v ds = 20v i d = 50a 09$%2/. 2* 60 40 20 0 20 40 60 80 100 120 140 160 t j , temperature ( c ) 40 42 44 46 48 50 v ( b r ) d s s , d r a i n t o s o u r c e b r e a k d o w n v o l t a g e ( v ) id = 1.0ma 0:$%'#)*. $ 0 200 400 600 800 1000 di f /dt (a/s) 0 1 2 3 4 5 6 7 i r r m ( a ) i f = 30a v r = 34v t j = 25c t j = 125c 011$%.%/. ; 0.0 0.4 0.8 1.2 1.6 2.0 v sd , sourcetodrain voltage (v) 1.0 10 100 1000 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 150c v gs = 0v 0 $%)* 75 50 25 0 25 50 75 100 125 150 t j , temperature ( c ) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) i d = 100a i d = 1.0ma i d = 1.0a 01$ *. $ 0 200 400 600 800 1000 di f /dt (a/s) 0 20 40 60 80 100 q r r ( n c ) i f = 30a v r = 34v t j = 25c t j = 125c 015$%.%/. $ downloaded from: http:///

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! ! " 3, 6, 8 com negative of gate drive supply voltage 2 v cc 15v gate drive supply 4 hin logic input for high side (active high) 5 lin logic input for low side (active high) 7 lo low side fet gate 9 g2 low side gate drive output 10, 16, 17 v s phase output 11 C 15 v low side source connection 18 C 23 v+ dc bus 24 g1 high side gate drive output 25 ho high side fet gate 26 C 27 v s negative of bootstrap supply 1 v b positive of bootstrap supply bottom of package view vb vcc com hin lin com lo 7 g2 9 vs v- 11 v- 12 v- 13 v- 14 16 vs v- 15 17 vs 18-v+ 19 20 v+ 21 v+ 22 v+ 23 v+ com 8 26 vs 24 g1 25 ho 27 vs v+ 10 1 2 3 4 5 6 $& 21&1+0.-2 < 1 % <&
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figure 13: typical application connection 1. bus capacitors should be mounted as close to the module bus terminals as possible to reduce ringing and emi problems. additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. 2. value of the bootstrap capacitors depends upon the switching frequency. their selection should be made based on ir design tip dt044 or application n ote an1044. 0 2 4 6 8 10 12 14 16 18 20 0.1 1 10 100 ser i es1 figure 14: typical output current (rms of fundamen tal) vs. modulation frequency sinusoidal modulation, v + =32v, t j =125c, t a =60c, mi=1, pf=0.8, mounted on 50 mm 2 of fr4 downloaded from: http:///

& &(. industrial ?? (per jedec jesd 47e) .%(. msl3 ??? (per ipc/jedec jstd020c) machine model class b (200v) (per jedec standard jesd22a115a) human body model class 1c (1000v) (per eia/jedec standard eia/jes001a2011)
/ yes ? qualification standards can be found at internation al rectifiers web site hu http://www.irf.com/ u ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative f or further information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. downloaded from: http:///

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!#<'*)?15> 1. for mounting instruction see an1178. 2. for recommended pcb via design see an1091. 3. for recommended design, solder profile, integrat ion and rework guidelines see an1028. 4. for board inspection guidelines see an1133. downloaded from: http:///

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data and specifications are subject to change witho ut notice @(
+&-+$a 233 kansas st., el segundo, california 90245, usa tel: (310) 2527105 tac fax: (310) 2527903 visit us at www.irf.com for sales contact informati on downloaded from: http:///

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